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X9523
Laser Diode Control for Fiber Optic Modules
Data Sheet March 10, 2005 FN8209.0
PRELIMINARY
Dual DCP, POR, Dual Voltage Monitors
FEATURES * Two Digitally Controlled Potentiometers (DCPs) --100 Tap - 10k --256 Tap - 100k --Nonvolatile --Write Protect Function * 2-Wire industry standard Serial Interface * Power-On Reset (POR) Circuitry --Programmable Threshold Voltage --Software Selectable reset timeout --Manual Reset * Two Supplementary Voltage Monitors --Programmable Threshold Voltages * Single Supply Operation --2.7V to 5.5V * Hot Pluggable * 20 Pin packages --XBGATM --TSSOP
DESCRIPTION The X9523 combines two Digitally Controlled Potentiometers (DCPs), V1 / Vcc Power-on Reset (POR) circuitry, qnd two programmable voltage monitor inputs with software and hardware indicators. All functions of the X9523 are accessed by an industry standard 2-Wire serial interface. The DCPs of the X9523 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module. The programmable POR circuit may be used to ensure that V1 / Vcc is stable before power is applied to the laser diode / module. The programmable voltage monitors may be used for monitoring various module alarm levels. The features of the X9523 are ideally suited to simplifying the design of fiber optic modules . The integration of these functions into one package significantly reduces board area, cost and increases reliability of laser diode modules.
BLOCK DIAGRAM
RH1
WIPER COUNTER REGISTER
RW1 RL1
WP
PROTECT LOGIC
7 - BIT NONVOLATILE MEMORY
SDA
DATA REGISTER
8
SCL
COMMAND DECODE & CONTROL LOGIC
CONSTAT
REGISTER
WIPER COUNTER REGISTER
RH2 RW2 RL2
8 - BIT NONVOLATILE MEMORY
THRESHOLD RESET LOGIC
MR V3
VTRIP3
2
+ + + POWER-ON / LOW VOLTAGE RESET GENERATION
V3RO
V2
VTRIP 2
V2RO
V1 / Vcc
VTRIP 1
V1RO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. (c)2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9523
DETAILED DEVICE DESCRIPTION The X9523 combines two Intersil Digitally Controlled Potentiometer (DCP) devices, V1/Vcc power-on reset control, V1/Vcc low voltage reset control, and two supplementary voltage monitors in one package. These functions are suited to the control, support, and monitoring of various system parameters in fiber optic modules. The combination of the X9523 fucntionality lowers system cost, increases reliability, and reduces board space requirements using Intersil's unique XBGATM packaging. Two high resolution DCPs allow for the "set-and-forget" adjustment of Laser Driver IC parameters such as Laser Diode Bias and Modulation Currents. Applying voltage to VCC activates the Power-on Reset circuit which allows the V1RO output to go HIGH, until the supply the supply voltage stabilizes for a period of time (selectable via software). The V1RO output then goes LOW. The Low Voltage Reset circuitry allows the V1RO output to go HIGH when VCC falls below the minimum VCC trip point. V1RO remains HIGH until VCC PIN CONFIGURATION
20 Pin TSSOP XBGA
returns to proper operating level. A Manual Reset (MR) input allows the user to externally trigger the V1RO output (HIGH). Two supplementary Voltage Monitor circuits continuously compare their inputs to individual trip voltages. If an input voltage exceeds it's associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input voltage becomes lower than it's associated trip level, the corresponding output is driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port. Intersil's unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field. The device features a 2-Wire interface and software protocol allowing operation on an I2CTM compatible serial bus.
RH2 RW2 RL2 V3 V3RO MR WP SCL SDA VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
V1 / Vcc V1RO V2RO V2 NC NC NC RH1 RW1 RL1
A B
1
2
3
4
V2RO V2 NC
V1 / Vcc RW2
RL2 V3 WP SCL SDA
V1RO NC NC RW1
RH2 V3RO MR RL1
C
RH1
D E
VSS
Top View - Bumps Down
NOT TO SCALE
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PIN ASSIGNMENT
Pin 1 2 3 4 XBGA B3 A3 A4 B4 Name RH2 Rw2 RL2 V3 Function Connection to end of resistor array for (the 256 Tap) DCP 2. Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 2. Connection to other end of resistor array for (the 256 Tap) DCP 2. V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the VTRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to VSS when not used. V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than VTRIP3 and goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external "pull-up" resistor. Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time tpurst after MR has returned to it's normally LOW state. The reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external "pull-down" resistor. Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile "write" operations. Also, when the Write Protection is enabled, and the device DCP Write Lock feature is active (i.e. the DCP Write Lock bit is "1"), then no "write" (volatile or nonvolatile) operations can be performedon the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal "pull-down" resistor, thus if left floating the write protection feature is disabled. Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. Ground. Connection to other end of resistor for (the 100 Tap) DCP 1. Connection to terminal equivalent to the "Wiper" of a mechanical potentiometer for DCP 1. Connection to end of resistor array for (the 100 Tap) DCP 1. V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the VTRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to VSS when not used. V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than VTRIP2, and goes LOW when V2 is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an external "pull-up" resistor. V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active whenever V1 / Vcc falls below VTRIP1. V1RO becomes active on power-up and remains active for a time tpurst after the power supply stabilizes (tpurst can be changed by varying the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an external "pull-up" resistor. The V1RO pin can be forced active (HIGH) using the manual reset (MR) input pin. Supply Voltage. No Connect.
5
C3
V3RO
6
D3
MR
7
C4
WP
8 9 10 11 12 13 17
D4 E4 E1 E3 E2 D1 B1
SCL SDA Vss RL1 Rw1 RH1 V2
18
A1
V2RO
19
B2
V1RO
20 14, 15, 16,
A2 C1, C2, D2
V1 / Vcc NC
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SCL
SDA Data Stable Figure 1. Data Change Data Stable
Valid Data Changes on the SDA Bus
PRINCIPLES OF OPERATION SERIAL INTERFACE
Serial Stop Condition
All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the X9523 operates as a slave in all applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKNOWLEDGE that it received the eight bits of data. Refer to Figure 3. The device will respond with an ACKNOWLEDGE after recognition of a START condition if the correct Device Identifier bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an ACKNOWLEDGE after the receipt of each subsequent eight bit word. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an ACKNOWLEDGE. If an ACKNOWLEDGE is detected and no STOP condition is generated by the master, the device will continue to transmit data. The device will ter-
Serial Clock and Data
Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 1.On power-up of the X9523, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. See Figure 2.
SCL SDA Start Figure 2.
4
Stop
Valid Start and Stop Conditions
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SCL from Master Data Output from Transmitter Data Output from Receiver
1
8
9
Start Figure 3.
Acknowledge Acknowledge Response From Receiver --The next three bits (SA3 - SA1) are the Internal Device Address bits. Setting these bits to 111 internally selects the DCP structures in the X9523. The CONSTAT Register may be selected using the Internal Device Address 010. --The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed on the device being addressed (as defined in the bits SA3 - SA1). When the R/W bit is "1", then a READ operation is selected. A "0" selects a WRITE operation (Refer to Figure 4.)
minate further data transmissions if an ACKNOWLEDGE is not detected. The master must then issue a STOP condition to place the device into a known state. DEVICE INTERNAL ADDRESSING Addressing Protocol Overview The user addressable internal components of the X9523 can be split up into two main parts: --Two Digitally Controlled Potentiometers (DCPs) --Control and Status (CONSTAT) Register Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9523 to be addressed, and specifies if a Read or Write operation is to be performed. It should be noted that in order to perform a write operation to a DCP, the Write Enable Latch (WEL) bit must first be set (See "WEL: Write Enable Latch (Volatile)" on page 10.). Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to Figure 4.). This byte consists of three parts: --The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier must always be set to 1010 in order to select the X9523.
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either the Non Volatile Memory of a DCP (NVM), or the CONSTAT Register) has been correctly issued (including the
SA7 SA6 SA5 SA4 SA3 SA2 SA1
SA0
101
DEVICE TYPE IDENTIFIER
0
INTERNAL DEVICE ADDRESS
R/W
READ / WRITE
Internal Address
(SA3 - SA1)
Internally Addressed Device CONSTAT Register DCP RESERVED
010 111 All Others
Bit SA0 0 1
Operation WRITE READ
Figure 4.
Slave Address Format
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final STOP condition), the X9523 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, no further Read or Write commands can be issued to the device. Write Acknowledge Polling is used to determine when this high voltage write cycle has been completed. To perform acknowledge polling, the master issues a START condition followed by a Slave Address Byte. The Slave Address issued must contain a valid Internal Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is still busy with the high voltage cycle then no ACKNOWLEDGE will be returned. If the device has completed the write operation, an ACKNOWLEDGE will be returned and the host can then proceed with a read or write operation. (Refer to Figure 5.).
Byte load completed by issuing STOP. Enter ACK Polling
WIPER COUNTER REGISTER (WCR) DECODER "WIPER" FET SWITCHES RESISTOR ARRAY
N
RHx
NON VOLATILE MEMORY (NVM)
2 1 0 RLx RWx
Figure 6.
DCP Internal Structure
Issue START
DIGITALLY CONTROLLED POTENTIOMETERS
Issue Slave Address Byte (Read or Write)
DCP Functionality
Issue STOP
ACK returned? YES High Voltage Cycle complete. Continue command sequence?
NO
The X9523 includes two independent resistor arrays. These arrays respectively contain 99 and 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RHx and RLx inputs - where x = 1,2). At both ends of each array and between each resistor segment there is a CMOS switch connected to the wiper (Rwx) output. Within each individual array, only one switch may be turned on at any one time. These switches are controlled by the Wiper Counter Register (WCR) (See Figure 6). The WCR is a volatile register. On power-up of the X9523, wiper position data is automatically loaded into the WCR from its associated Non Volatile Memory (NVM) Register. The Table below shows the Initial Values of the DCP WCR's before the contents of the NVM is loaded into the WCR.
DCP R1 / 100 TAP Initial Values Before Recall VL / TAP = 0 VH / TAP = 255
NO Issue STOP
YES Continue normal Read or Write command sequence
PROCEED
Figure 5.
Acknowledge Polling Sequence
R2 / 256 TAP
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V1/Vcc
V1/Vcc (Max.) VTRIP1
ttrans
tpurst
t
0
Maximum Wiper Recall time
Figure 7. The data in the WCR is then decoded to select and enable one of the respective FET switches. A "make before break" sequence is used internally for the FET switches when the wiper is moved from one tap position to another.
DCP Power-up A volatile write operation to a DCP however, changes the "wiper position" by writing new data to the associated WCR only. The contents of the associated NVM register remains unchanged. Therefore, when V1/Vcc to the device is powered down then back up, the "wiper position" reverts to that last position written to the DCP using a nonvolatile write operation. Both volatile and nonvolatile write operations are executed using a three byte command sequence: (DCP) Slave Address Byte, Instruction Byte, followed by a Data Byte (See Figure 9) A DCP Read operation allows the user to "read out" the current "wiper position" of the DCP, as stored in the associated WCR. This operation is executed using the Random Address Read command sequence, consisting of the (DCP) Slave Address Byte followed by an Instruction Byte and the Slave Address Byte again (Refer to Figure 10.).
Hot Pluggability
Figure 7 shows a typical waveform that the X9523 might experience in a Hot Pluggable situation. On power-up, V1 / Vcc applied to the X9523 may exhibit some amount of ringing, before it settles to the required value. The device is designed such that the wiper terminal (RWx) is recalled to the correct position (as per the last stored in the DCP NVM), when the voltage applied to V1/Vcc exceeds VTRIP1 for a time exceeding tpurst (the Power-on Reset time, set in the CONSTAT Register See "CONTROL AND STATUS REGISTER" on page 10.). Therefore, if ttrans is defined as the time taken for V1 / Vcc to settle above VTRIP1 (Figure 7): then the desired wiper terminal position is recalled by (a maximum) time: ttrans + tpurst. It should be noted that ttrans is determined by system hot plug conditions.
Instruction Byte
While the Slave Address Byte is used to select the DCP devices, an Instruction Byte is used to determine which DCP is being addressed. The Instruction Byte (Figure 8) is valid only when the Device Type Identifier and the Internal Device Address bits of the Slave Address are set to 1010111. In this case, the two Least Significant Bit's (I1 - I0) of the Instruction Byte are used to select the particular DCP (0 - 2). In the case of a Write to any of the DCPs (i.e. the LSB of the Slave Address is 0), the Most Significant Bit of the Instruction Byte (I7), determines the Write Type (WT) performed. If WT is "1", then a Nonvolatile Write to the DCP occurs. In this case, the "wiper position" of the DCP is changed by simultaneously writing new data to the associated
DCP Operations
In total there are three operations that can be performed on any internal DCP structure: --DCP Nonvolatile Write --DCP Volatile Write --DCP Read A nonvolatile write to a DCP will change the "wiper position" by simultaneously writing new data to the associated WCR and NVM. Therefore, the new "wiper position" setting is recalled into the WCR after V1/Vcc of the X9523 is powered down and then powered back up.
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I7
WT
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
WRITE TYPE
DCP SELECT
Next, an Instruction Byte is issued on SDA. Bits P1 and P0 of the Instruction Byte determine which WCR is to be written, while the WT bit determines if the Write is to be volatile or nonvolatile. If the Instruction Byte format is valid, another ACKNOWLEDGE is then returned by the X9523. Following the Instruction Byte, a Data Byte is issued to the X9523 over SDA. The Data Byte contents is latched into the WCR of the DCP on the first rising edge of the clock signal, after the LSB of the Data Byte (D0) has been issued on SDA (See Figure 29). The Data Byte determines the "wiper position" (which FET switch of the DCP resistive array is switched ON) of the DCP. The maximum value for the Data Byte depends upon which DCP is being addressed (see Table below).
P1- P0 DCPx x=1 x=2 # Taps 100 256 RESERVED Max. Data Byte Refer to Appendix 1 FFh
WT 0 1
Description Select a Volatile Write operation to be performed on the DCP pointed to by bits P1 and P0 Select a Nonvolatile Write operation to be performed on the DCP pointed to by bits P1 and P0
This bit has no effect when a Read operation is being performed.
Figure 8.
Instruction Byte Format
WCR and NVM. Therefore, the new "wiper position" setting is recalled into the WCR after V1/Vcc of the X9523 has been powered down then powered back up. If WT is "0" then a DCP Volatile Write is performed. This operation changes the DCP "wiper position" by writing new data to the associated WCR only. The contents of the associated NVM register remains unchanged. Therefore, when V1/Vcc to the device is powered down then back up, the "wiper position" reverts to that last written to the DCP using a nonvolatile write operation.
0 0 1 1
0 1 0 1
RESERVED
Using a Data Byte larger than the values specified above results in the "wiper terminal" being set to the highest tap position. The "wiper position" does NOT roll-over to the lowest tap position. For DCP2 (256 Tap), the Data Byte maps one to one to the "wiper position" of the DCP "wiper terminal". Therefore, the Data Byte 00001111 (1510) corresponds to setting the "wiper terminal" to tap position 15. Similarly, the Data Byte 00011100 (2810) corresponds to setting the "wiper terminal" to tap position 28. The mapping of the Data Byte to "wiper position" data for DCP1 (100 Tap), is shown in "APPENDIX 1". An example of a simple C language function which "translates" between the tap position (decimal) and the Data Byte (binary) for DCP1, is given in "APPENDIX 2".
DCP Write Operation
A write to DCPx (x = 1,2) can be performed using the three byte command sequence shown in Figure 9. In order to perform a write operation on a particular DCP, the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See "WEL: Write Enable Latch (Volatile)" on page 10.). The Slave Address Byte 10101110 specifies that a Write to a DCP is to be conducted. An ACKNOWLEDGE is returned by the X9523 after the Slave Address, if it has been received correctly.
S1 T A R T
0
1
0
1
1
1
0
A WT C K
0
0
0
0
0
P1 P0
A C K
D7 D6 D5 D4 D3 D2 D1 D0
A C K
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
S T O P
Figure 9.
DCP Write Command Sequence
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WRITE Operation
Signals from the Master
S t a r t
Slave Address
Instruction Byte
S t a r t
READ Operation
Slave Address
Data Byte
S t o p
SDA Bus Signals from the Slave
10101110
A C K
W 00000 P P 10 T
A C K
10101111
A C K
-
DCPx x=1 x=2
MSB LSB
"Dummy" write
Figure 10.
DCP Read Sequence
"-" = DON'T CARE
It should be noted that all writes to any DCP of the X9523 are random in nature. Therefore, the Data Byte of consecutive write operations to any DCP can differ by an arbitrary number of bits. Also, setting the bits P1 = 1, P0 = 1 is a reserved sequence, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA. The factory default setting of all "wiper position" settings is with 00h stored in the NVM of the DCPs. This corresponds to having the "wiper teminal" RWX (x = 1,2) at the "lowest" tap position, Therefore, the resistance between RWX and RLX is a minimum (essentially only the Wiper Resistance, RW).
The master issues the START condition and the Slave Address Byte 10101110 which specifies that a "dummy" write" is to be conducted. This "dummy" write operation sets which DCP is to be read (in the preceding Read operation). An ACKNOWLEDGE is returned by the X9523 after the Slave Address if received correctly. Next, an Instruction Byte is issued on SDA. Bits P1-P0 of the Instruction Byte determine which DCP "wiper position" is to be read. In this case, the state of the WT bit is "don't care". If the Instruction Byte format is valid, then another ACKNOWLEDGE is returned by the X9523. Following this ACKNOWLEDGE, the master immediately issues another START condition and a valid Slave address byte with the R/W bit set to 1. Then the X9523 issues an ACKNOWLEDGE followed by Data Byte, and finally, the master issues a STOP condition. The Data Byte read in this operation, corresponds to the "wiper position" (value of the WCR) of the DCP pointed to by bits P1 and P0.
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the three byte random read command sequence shown in Figure 10.
Signals from the Master
S t a r t
WRITE Operation
Slave Address
Address Byte
Data Byte
S t o p
SDA Bus Signals from the Slave
1 01 00 00 0
Internal Device Address
A C K
A C K
A C K
Figure 11. EEPROM Byte Write Sequence
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The WEL bit is a volatile latch that powers up in the disabled, LOW (0) state. The WEL bit is enabled / set by writing 00000010 to the CONSTAT register. Once enabled, the WEL bit remains set to "1" until either it is reset to "0" (by writing 00000000 to the CONSTAT register) or until the X9523 powers down, and then up again. Writes to the WEL bit do not cause an internal high voltage write cycle. Therefore, the device is ready for another operation immediately after a STOP condition is executed in the CONSTAT Write command sequence (See Figure 13). RWEL: Register Write Enable Latch (Volatile) The RWEL bit controls the (CONSTAT) Register Write Enable status of the X9523. Therefore, in order to write to any of the bits of the CONSTAT Register (except WEL), the RWEL bit must first be set to "1". The RWEL bit is a volatile bit that powers up in the disabled, LOW ("0") state. It must be noted that the RWEL bit can only be set, once the WEL bit has first been enabled (See "CONSTAT Register Write Operation"). The RWEL bit will reset itself to the default "0" state, in one of two cases: --After a successful write operation to any bits of the CONSTAT register has been completed (See Figure 13). --When the X9523 is powered down. DWLK: DCP Write Lock bit - (Nonvolatile) The DCP Write Lock bit (DWLK) is used to inhibit a DCP write operation (changing the "wiper position"). When the DCP Write Lock bit of the CONSTAT register is set to "1", then the "wiper position" of the DCPs cannot be changed - i.e. DCP write operations cannot be conducted:
DWLK 0 1 DCP Write Operation Permissible YES (Default) NO
CS7
POR1 NV
CS6
V2OS
CS5
V3OS
CS4
CS3
DWLK NV
CS2
RWEL
CS1
WEL
CS0
POR0 NV
0
Bit(s) POR1 V2OS V1OS CS4 DWLK RWEL WEL POR0
Description Power-on Reset bit V2 Output Status flag V1 Output Status flag Always set to "0" (RESERVED) Sets the DCP Write Lock Register Write Enable Latch bit Write Enable Latch bit Power-on Reset bit
NOTE: Bits labelled NV are nonvolatile (See "CONTROL AND STATUS REGISTER").
Figure 12. CONSTAT Register Format It should be noted that when reading out the data byte for DCP1 (100 Tap), the upper most significant bit is an "unknown". For DCP2 (256 Tap) however, all bits of the data byte are relevant (See Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register provides the user with a mechanism for changing and reading the status of various parameters of the X9523 (See Figure 12). The CONSTAT register is a combination of both volatile and nonvolatile bits. The nonvolatile bits of the CONSTAT register retain their stored values even when V1/Vcc is powered down, then powered back up. The volatile bits however, will always power-up to a known logic state "0" (irrespective of their value at power-down). A detailed description of the function of each of the CONSTAT register bits follows: WEL: Write Enable Latch (Volatile) The WEL bit controls the Write Enable status of the entire X9523 device. This bit must first be enabled before ANY write operation (to DCPs, or the CONSTAT register). If the WEL bit is not first enabled, then ANY proceeding (volatile or nonvolatile) write operation to DCPs or the CONSTAT register, is aborted and no ACKNOWLEDGE is issued after a Data Byte.
The factory default setting for this bit is DWLK = 0. IMPORTANT NOTE: If the Write Protect (WP) pin of the X9523 is active (HIGH), then nonvolatile write operations to the DCPs are inhibited, irrespective of the DCP Write Lock bit setting (See "WP: Write Protection Pin").
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SCL
SDA S T A R T 1 0 1 0 0 1 0 R/W A C K 1 1 1 1 1 1 1 1 A C K CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 A C K S T O P
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 13. CONSTAT Register Write Command Sequence
POR1, POR0: Power-on Reset bits - (Nonvolatile) Applying voltage to VCC activates the Power-on Reset circuit which holds V1RO output HIGH, until the supply voltage stabilizes above the VTRIP1 threshold for a period of time, tPURST (See Figure 25). The Power-on Reset bits, POR1 and POR0 of the CONSTAT register determine the tPURST delay time of the Power-on Reset circuitry (See "VOLTAGE MONITORING FUNCTIONS"). These bits of the CONSTAT register are nonvolatile, and therefore power-up to the last written state. The nominal Power-on Reset delay time can be selected from the following table, by writing the appropriate bits to the CONSTAT register:
POR1 0 0 1 1 POR0 0 1 0 1 Power-on Reset delay (tPUV1RO) 50ms 100ms (Default) 200ms 300ms
Once the VxOS bits have been set to "1", they will be reset to "0" if: --The device is powered down, then back up, --The corresponding VxRO output becomes LOW.
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave Address set to 1010010 (Refer to Figure 4.). Following the Slave Address Byte, access to the CONSTAT register requires an Address Byte which must be set to FFh. Only one data byte is allowed to be written for each CONSTAT register Write operation. The user must issue a STOP, after sending this byte to the register, to initiate the nonvolatile cycle that stores the DWLK, POR1 and POR0 bits. The X9523 will not ACKNOWLEDGE any data bytes written after the first byte is entered (Refer to Figure 13.). When writing to the CONSTAT register, the bit CS4 must always be set to "0". Writing a "1" to bit CS4 of the CONSTAT register is a reserved operation. Prior to writing to the CONSTAT register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps --Write a 02H to the CONSTAT Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a START and ended with a STOP). --Write a 06H to the CONSTAT Register to set the Register Write Enable Latch (RWEL) AND the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceded by a START and ended with a STOP).
The default for these bits are POR1 = 0, POR0 = 1. V2OS, V3OS: Voltage Monitor Status Bits (Volatile) Bits V2OS and V3OS of the CONSTAT register are latched, volatile flag bits which indicate the status of the Voltage Monitor reset output pins V2RO and V3RO. At power-up the VxOS (x = 2,3) bits default to the value "0". These bits can be set to a "1" by writing the appropriate value to the CONSTAT register. To provide consistency between the VxRO and VxOS however, the status of the VxOS bits can only be set to a "1" when the corresponding VxRO output is HIGH.
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X9523
READ Operation
Signals from the Master
S t a r t
WRITE Operation
Slave Address
Address Byte
S t Slave a r Address t 10 1 0 0 1 01
S t o p CS7 ... CS0 A C K
SDA Bus Signals from the Slave
10 1 0 0 1 0 0 A C K
"Dummy" Write
A C K
Data
Figure 14. CONSTAT Register Read Command Sequence
--Write a one byte value to the CONSTAT Register that has all the bits set to the desired state. The CONSTAT register can be represented as qxyst01r in binary, where xy are the Voltage Monitor Output Status (V2OS and V3OS) bits, t is the DCP Write Lock (DWLK) bit, and qr are the Power-on Reset delay time (tPUV1RO) control bits (POR1 - POR0). This operation is proceeded by a START and ended with a STOP bit. Since this is a nonvolatile write cycle, it will typically take 5ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to `1' in this third step (qxys t11r) then the RWEL bit is set, but the V2OS, V3OS, POR1, POR0, and DWLK bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and the X9523 does not return an ACKNOWLEDGE. For example, a sequence of writes to the device CONSTAT register consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the CONSTAT Register to "0". It should be noted that a write to any nonvolatile bit of CONSTAT register will be ignored if the Write Protect pin of the X9523 is active (HIGH) (See "WP: Write Protection Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at any time by performing a random read (See Figure 14). Using the Slave Address Byte set to 10100101, and an Address Byte of FFh. Only one byte is read by each register read operation. The X9523 resets itself after the first byte is read. The master should supply a STOP condition to be consistent with the bus protocol. After setting the WEL and / or the RWEL bit(s) to a "1", a CONSTAT register read operation may occur, without interrupting a proceeding CONSTAT register write operation. When performing a read operation on the CONSTAT registerm, bit CS4 will always return a "0" value. DATA PROTECTION There are a number of levels of data protection features designed into the X9523. Any write to the device first requires setting of the WEL bit in the CONSTAT register. A write to the CONSTAT register itself, further requires the setting of the RWEL bit. DCP Write Lock protection of the device enables the user to inhibit writes to all the DCPs. One further level of data protection in the X9523, is incorporated in the form of the Write Protection pin.
X9522 Write Permission Status
DWLK (DCP Write Lock bit status) 1 0 1 0 WP (Write Protect pin status) 1 1 DCP Volatile Write Permitted NO YES NO YES DCP Nonvolatile Write Permitted NO NO NO YES Write to CONSTAT Register Permitted Volatile Bits NO NO YES YES Nonvolatile Bits NO NO YES YES
0 0
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WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it disables nonvolatile write operations to the X9523. The table below (X9523 Write Permission Status) summarizes the effect of the WP pin (and DCP Write Lock), on the write permission status of the device.
Vx
VTRIPx
0V
VxRO
0V
Additional Data Protection Features
In addition to the preceding features, the X9523 also incorporates the following data protection functionality:
V1 / Vcc VTRIP1
0 Volts (x = 2,3)
--The proper clock count and data bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle.
Figure 16. Voltage Monitor Response
VOLTAGE MONITORING FUNCTIONS
V1 / Vcc Monitoring
The X9523 monitors the supply voltage and drives the V1RO output HIGH (using an external "pull up" resistor) if V1/Vcc is lower than VTRIP1 threshold. The V1RO output will remain HIGH until V1/Vcc exceeds VTRIP1 for a minimum time of tPURST. After this time, the V1RO pin is driven to a LOW state. See Figure 25. For the Power-on/Low Voltage Reset function of the X9523, the V1RO output may be driven HIGH down to a V1/Vcc of 1V (VRVALID). See Figure 25. Another feature of the X9523, is that the value of tPURST may be selected in software via the CONSTAT register (See "POR1, POR0: Power-on Reset bits - (Nonvolatile)" on page 11.).
It is recommended to stop communication to the device while while V1RO is HIGH. Also, setting the Manual Reset (MR) pin HIGH overrides the Power-on/Low Voltage circuitry and forces the V1RO output pin HIGH (See "Manual Reset").
Manual Reset
The V1RO output can be forced HIGH externally using the Manual Reset (MR) input. MR is a de-bounced, TTL compatible input, and so it may be operated by connecting a push-button directly from V1/Vcc to the MR pin. V1RO remains HIGH for time tPURST after MR has returned to its LOW state (See Figure 15). An external "pull down" resistor is required to hold this pin (normally) LOW.
V1 / Vcc
0 Volts
VTRIP1
V2 monitoring
The X9523 asserts the V2RO output HIGH if the voltage V2 exceeds the corresponding VTRIP2 threshold (See Figure 16). The bit V2OS in the CONSTAT register is then set to a "0" (assuming that it has been set to "1" after system initilization). The V2RO output may remain active HIGH with VCC down to 1V.
MR
0 Volts
V1RO
0 Volts
tPURST Figure 15. Manual Reset Response
V3 monitoring
The X9523 asserts the V3RO output HIGH if the voltage V3 exceeds the corresponding VTRIP3 threshold (See Figure 16). The bit V3OS in the CONSTAT register is then set to a "0" (assuming that it has been set to "1" after system initilization). The V3RO output may remain active HIGH with VCC down to 1V.
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V1 / Vcc V2, V3
VTRIPx
VP WP
01234567
SCL
01234567
01234567
SDA
00h A0h
S T A R T
01h sets VTRIP1 09h sets VTRIP2 0Dh sets V
TRIP3
Data Byte
All others Reserved.
Figure 17. Setting VTRIPx to a higher level (x = 1,2,3).
VTRIPX THRESHOLDS (X = 1,2,3) The X9523 is shipped with pre-programmed threshold (VTRIPx) voltages. In applications where the required thresholds are different from the default values, or if a higher precision/tolerance is required, the X9523 trip points may be adjusted by the user, using the steps detailed below.
Setting a Higher VTRIPx Voltage (x = 1,2,3)
To set a VTRIPx threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIPx threshold voltage to the corresponding input pin (V1/Vcc, V2 or V3). Then, a programming voltage (Vp) must be applied to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for VTRIP1, 09h for VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order to program VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to complete the operation (See Figure 18). The user does not have to set the WEL bit in the CONSTAT register before performing this write sequence.
Setting a VTRIPx Voltage (x = 1,2,3)
There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIPx is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the VTRIPx cell. If however, the new setting is to be lower than the present setting, then it is necessary to "reset" the VTRIPx voltage before setting the new value.
VP WP
01234567
SCL
01234567
01234567
SDA
00h A0h
S T A R T
03h Resets VTRIP1 0Bh Resets VTRIP2 0Fh Resets VTRIP3
Data Byte
Figure 18. Resetting the VTRIPx Level
All others Reserved.
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Setting a Lower VTRIPx Voltage (x = 1,2,3). In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be "reset" according to the procedure described below. Once VTRIPx has been "reset", then VTRIPx can be set to the desired voltage using the procedure described in "Setting a Higher VTRIPx Voltage". After applying the test voltage to the voltage monitor input pin, the test voltage can be decreased (either in discrete steps, or continuously) until the output of the voltage monitor circuit changes state. At this point, the error between the actua measured, and desired threshold levels is calculated. For example, the desired threshold for VTRIP2 is set to 3.0V, and a test voltage of 3.4V was applied to the input pin V2 (after applying power to V1/Vcc). The input voltage is decreased, and found to trip the associated output level of pin V2RO from a LOW to a HIGH, when V2 reaches 3.09V. From this, it can be calculated that the programming error is 3.09 - 3.0 = 0.09V. If the error between the desired and measured VTRIPx is less than the maximum desired error, then the programming process may be terminated. If however, the error is greater than the maximum desired error, then another iteration of the VTRIPx programming sequence can be performed (using the calculated error) in order to further increase the accuracy of the threshold voltage. If the calculated error is greater than zero, then the VTRIPx must first be "reset", and then programmed to the a value equal to the previously set VTRIPx minus the calculated error. If it is the case that the error is less than zero, then the VTRIPx must be programmed to a value equal to the previously set VTRIPx plus the absolute value of the calculated error. Continuing the previous example, we see that the calculated error was 0.09V. Since this is greater than zero, we must first "reset" the VTRIP2 threshold, then apply a voltage equal to the last previously programmed voltage, minus the last previously calculated error. Therefore, we must apply VTRIP2 = 2.91 V to pin V2 and execute the programming sequence (See "Setting a Higher VTRIPx Voltage (x = 1,2,3)" ) . Using this process, the desired accuracy for a particular VTRIPx threshold may be attained using a successive number of iterations.
Resetting the VTRIPx Voltage (x = 1,2,3).
To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for VTRIP1, 0Bh for VTRIP2, and 0Fh for VTRIP3, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to complete the operation (See Figure 18).The user does not have to set the WEL bit in the CONSTAT register before performing this write sequence. After being reset, the value of VTRIPx becomes a nominal value of 1.7V.
VTRIPx Accuracy (x = 1,2,3).
The accuracy with which the VTRIPx thresholds are set, can be controlled using the iterative process shown in Figure 19. If the desired threshold is less that the present threshold voltage, then it must first be "reset" (See "Resetting the VTRIPx Voltage (x = 1,2,3)." ) . The desired threshold voltage is then applied to the appropriate input pin (V1/Vcc, V2 or V3) and the procedure described in Section "Setting a Higher VTRIPx Voltage" must be followed. Once the desired VTRIPx threshold has been set, the error between the desired and (new) actual set threshold can be determined. This is achieved by applying V1/Vcc to the device, and then applying a test voltage higher than the desired threshold voltage, to the input pin of the voltage monitor circuit whose VTRIPx was programmed. For example, if VTRIP2 was set to a desired level of 3.0V, then a test voltage of 3.4 V may be applied to the voltage monitor input pin V2. In the case of setting of VTRIP1 then only V1/Vcc need be applied. In all cases, care should be taken not to exceed the maximum input voltage limits.
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Note: X = 1,2,3. Let: MDE = Maximum Desired Error
VTRIPx Programming
NO
Desired VTRIPx < present value?
YES Execute VTRIPx Reset Sequence Set Vx = desired VTRIPx Execute Set Higher VTRIPx Sequence
MDE+ Desired Value MDE- Error = Actual - Desired Acceptable Error Range
New Vx applied = Old Vx applied + | Error |
New Vx applied = Old Vx applied - | Error |
Apply Vcc & Voltage > Desired VTRIPx to Vx
Execute Reset VTRIPx Sequence
Decrease Vx
NO
Output switches?
YES
Error < MDE-
- Desired VTRIPx
= Error
Actual VTRIPx
Error >MDE+
| Error | < | MDE |
DONE
Figure 19. VTRIPx Setting / Reset Sequence (x = 1,2,3)
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ABSOLUTE MAXIMUM RATINGS
Parameter Min. Max. Units
Temperature under Bias Storage Temperature Voltage on WP pin (With respect to Vss) Voltage on other pins (With respect to Vss) | Voltage on RHx - Voltage on RLx | (x = 0,1,2. Referenced to Vss) D.C. Output Current (SDA,V1RO,V2RO,V3RO) Lead Temperature (Soldering, 10 seconds) Supply Voltage Limits (Applied V1/Vcc voltage, referenced to Vss) RECOMMENDED OPERATING CONDITIONS
Temperature Commercial Industrial
-65 -65 -1.0 -1.0
0
2.7
+135 +150 +15 +7 V1/Vcc 5 300 5.5
C C V V V mA C V
Min. 0 -40
Max. 70 +85
Units
C C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Figure 20. Equivalent A.C. Circuit
V1 / Vcc = 5V
2300 SDA
V2RO V3RO V1RO
100pF
Figure 21. DCP SPICE Macromodel
RTOTAL RHx CH 10pF RW CW 25pF RWx CL 10pF RLx
(x=0,1,2)
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TIMING DIAGRAMS Figure 22. Bus Timing tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tAA tDH SDA OUT tBUF tSU:STO tHIGH tLOW tR
Figure 23. WP Pin Timing START SCL Clk 1 Clk 9
SDA IN WP tSU:WP tHD:WP
Figure 24. Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK tWC Stop Condition Start Condition
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Figure 25. Power-Up and Power-Down Timing t V1/Vcc 0 Volts t V1RO 0 Volts MR
PURST
R
tF V TRIP1 t tRPD
PURST
0 Volts
Figure 26. Manual Reset Timing Diagram
MR
0 Volts V1RO 0 Volts tMRD
tMRPW
t
PURST
V1 / Vcc
V1/Vcc V TRIP1
Figure 27. V2, V3 Timing Diagram t Vx tRPDx tRPDx 0 Volts tRPDx VxRO Rx tFx V TRIPx tRPDx
0 Volts V1/Vcc V TRIP1 V Note : x = 2,3. RVALID 0 Volts
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Figure 28. VTRIPX Programming Timing Diagram (x = 1,2,3).
V Vcc, V2, V3
VTRIPx
tTSU
tTHD
VP
WP
tVPS tVPO
SCL
twc SDA 00h
NOTE : V1/Vcc must be greater than V2, V3 when programming. Figure 29. DCP "Wiper Position" Timing
Rwx (x = 0,1,2)
tVPH
Rwx(n)
Rwx(n + 1) Rwx(n - 1)
twr
n = tap position
SCL
Time
SDA
S1 T A R T 0 1 0 1 1 1 0 A WT C K 0 0 0 0 0 P1 P0 A C K D7 D6 D5 D4 D3 D2 D1 D0 A C K S T O P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
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D.C. OPERATING CHARACTERISTICS
Symbol ICC1(1) Parameter Current into VCC Pin (X9523: Active) Read memory array (3) Write nonvolatile memory Current into VCC Pin ICC2(2) (X9523:Standby) With 2-Wire bus activity (3) No 2-Wire bus activity Input Leakage Current (SCL, SDA, MR) Input Leakage Current (WP) Analog Input Leakage Output Leakage Current (SDA, V1RO, V2RO, V3RO) VTRIP1 Programming Range VTRIPx Programming Range (x = 2,3) Pre - programmed VTRIP1 threshold Pre - programmed VTRIP2 threshold Pre - programmed VTRIP3 threshold V2 Input leakage current V3 Input leakage current Input LOW Voltage (SCL, SDA, WP, MR) Input HIGH Voltage (SCL,SDA, WP, MR) V1RO, V2RO, V3RO, SDA Output Low Voltage -0.5 2.0 2.75 1.8 2.85 4.55 1.65 2.85 1.65 2.85 3.0 4.7 1.8 3.0 1.8 3.0 1 0.1 0.1 50 50 10 10 10 10 4.70 4.70 3.05 4.75 1.85 3.05 1.85 3.05 1 1 0.8 VCC +0.5 0.4 A 0.4 1.5 mA fSCL = 400kHz VSDA = VCC MR = Vss WP = Vss or Open/Floating VSCL= VCC (when no bus activity else fSCL = 400kHz) VIN (4) = GND to VCC. VIN = VSS to VCC with all other analog pins floating VOUT (5) = GND to VCC. X9523 is in Standby(2) Min Typ Max Unit Test Conditions / Notes
ILI Iai ILO VTRIP1PR VTRIPxPR VTRIP1 (6) VTRIP2 (6) VTRIP3 (6) IVx VIL (7) VIH (7) VOLx
A A A A V V V V V A V V V
Factory shipped default option A Factory shipped default option B Factory shipped default option A Factory shipped default option B Factory shipped default option A Factory shipped default option B VSDA = VSCL = VCC Others=GND or VCC
ISINK = 2.0mA
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation. Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte. Notes: 3. Current through external pull up resistor not included. Notes: 4. VIN = Voltage applied to input pin. Notes: 5. VOUT = Voltage applied to output pin. Notes: 6. See "ORDERING INFORMATION" on page 30. Notes: 7. VIL Min. and VIH Max. are for reference only and are not tested
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A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
400kHz Symbol fSCL tIN(5) tAA(5) tBUF(5) tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH
(5)
Parameter SCL Clock Frequency Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid Time the bus free before start of new transmission Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time WP Setup Time WP Hold Time Capacitive load for each bus line
Min 0 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 +.1Cb (2) 20 +.1Cb 0.6 0
(2)
Max 400
Units kHz ns
0.9
s s s s s s ns s s ns
tR (5) tF
(5)
300 300
ns ns s s
tSU:WP tHD:WP Cb(5)
400
pF
A.C. TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load 0.1VCC to 0.9VCC 10ns 0.5VCC See Figure 20
NONVOLATILE WRITE CYCLE TIMING
Symbol tWC(4) Parameter Nonvolatile Write Cycle Time Min. Typ.(1) 5 Max. 10 Units ms
CAPACITANCE (TA = 25C, F = 1.0 MHZ, VCC = 5V)
Symbol COUT
(5)
Parameter Output Capacitance (SDA, V1RO, V2RO, V3RO) Input Capacitance (SCL, WP, MR)
Max 8 6
Units pF pF
Test Conditions VOUT = 0V VIN = 0V
CIN (5)
Notes: 1. Typical values are for TA = 25C and VCC = 5.0V Notes: 2. Cb = total capacitance of one bus line in pF. Notes: 3. Over recommended operating conditions, unless otherwise specified Notes: 4. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Notes: 5. This parameter is not 100% tested.
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POTENTIOMETER CHARACTERISTICS
Limits Symbol RTOL VRHx VRLx PR Parameter End to End Resistance Tolerance RH Terminal Voltage (x = 0,1,2) RL Terminal Voltage (x = 0,1,2) Power Rating (1)(6) 200 RW DCP Wiper Resistance 400 IW Wiper Current (6) 1200 4.4 mA mV/ sqt(Hz) mV/ sqt(Hz) -1 -1 300 300 10/10/25 200 +1 +1 MI(4) MI(4) ppm/C ppm/C pF s RTOTAL = 10k (DCP0, DCP1) RTOTAL = 100k (DCP2) Rw(n)(actual) - Rw(n)(expected) Rw(n + 1) - [Rw(n) + MI] RTOTAL = 10k (DCP0, DCP1) RTOTAL = 100k (DCP2) See Figure 21. See Figure 29. Min. -20 Vss Vss Typ. Max. +20 VCC VCC 10 5 400 Units % V V mW mW RTOTAL = 10k (DCP0, DCP1) RTOTAL = 100k (DCP2) IW = 1mA, VCC = 5V, VRHx = Vcc, VRLx = Vss (x = 0,1,2). IW = 1mA, VCC = 2.7V, VRHx = Vcc, VRLx = Vss (x = 0,1,2) Test Conditions/Notes
Noise
Absolute Linearity (2) Relative Linearity (3) RTOTAL Temperature Coefficient CH/CL/CW twr Potentiometer Capacitances Wiper Response time(6)
Notes: 1. Power Rating between the wiper terminal RWX(n) and the end terminals RHX or RLX - for ANY tap position n, (x = 0,1,2). Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (Rwx(n)(actual) - Rwx(n)(expected)) = 1 Ml Maximum (x = 0,1,2). Notes: 3. Relative Linearity is a measure of the error in step size between taps = RWx(n+1) - [Rwx(n) + Ml] = 1 Ml (x = 0,1,2) Notes: 4. 1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1). Notes: 5. Typical values are for TA = 25C and nominal supply voltage. Notes: 6. This parameter is periodically sampled and not 100% tested.
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VTRIPX (X = 1,2,3) PROGRAMMING PARAMETERS (See Figure 28)
Parameter tVPS tVPH tTSU tTHD tVPO twc VP Vta Vtv
Notes:
Description VTRIPx Program Enable Voltage Setup time VTRIPx Program Enable Voltage Hold time VTRIPx Setup time VTRIPx Hold (stable) time VTRIPx Program Enable Voltage Off time (Between successive adjustments) VTRIPx Write Cycle time Programming Voltage VTRIPx Program Voltage accuracy (Programmed at 25oC.) VTRIP Program variation after programming (-40 - 85oC). (Programmed at 25oC.)
Min 10 10 10 10 1
Typ
Max
Units s s s s ms
5 10 -100 -25 +10
10 15 +100 +25
ms V mV mV
The above parameters are not 100% tested.
V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 25, Figure 26, Figure 27)
Symbol Description Condition POR1 = 0, POR0 = 0 tPURST(5) Power-on Reset delay time POR1 = 0, POR0 = 1 POR1 = 1, POR0 = 0 POR1 = 1, POR0 = 1 tMRD (26)(2)(5) tMRDPW(5) tRPDx(5) tFx(5) tRx(5) VRVALID(5) MR to V1RO propagation delay MR pulse width V Vcc, V2, V3 to V1RO, V2RO, V3RO propagation delay (respectively) V1/Vcc, V2, V3 Fall Time V1/Vcc, V2, V3 Rise Time V1/Vcc for V1RO, V2RO, V3RO Valid (3). 20 20 1 See (1)(2)(4) 500 20 Min. 25 50 100 150 Typ. 50 100 200 300 Max. 75 150 300 450 5 Units ms ms ms ms s ns s mV/s mV/s V
Notes: 1. See Figure 26 for timing diagram. Notes: 2. See Figure 20 for equivalent load. Notes: 3. This parameter describes the lowest possible V1/Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to their inputs (V1/Vcc, V2, V3). Notes: 4. From MR rising edge crossing VIH, to V1RO rising edge crossing VOH. Notes: 5. The above parameters are not 100% tested.
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APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Tap Position 0 1 . . 23 24 25 26 . . 48 49 50 51 . . 73 74 75 76 . . 98 99 Data Byte Decimal 0 1 . . 23 24 56 55 . . 33 32 64 65 . . 87 88 120 119 . . 97 96 Binary 0000 0000 0000 0001 . . 0001 0111 0001 1000 0011 1000 0011 0111 . . 0010 0001 0010 0000 0100 0000 0100 0001 . . 0101 0111 0101 1000 0111 1000 0111 0111 . . 0110 0001 0110 0000
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APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned { int int int int
DCP1_TAP_Position(int tap_pos) block; i; offset; wcr_val;
offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): { wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } case (2): { wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); } case (3): { wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); }
}
} return((unsigned)01100000);
}
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FN8209.0 March 10, 2005
X9523
APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos) { /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); else if (tap_pos >99) return ((unsigned) 96); /* 100 Tap DCP encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); }
/* set to min val */ /* set to max val */
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FN8209.0 March 10, 2005
X9523
20 Ball BGA (X9523)
a a l j
m
1 A B 2 3 4 4 3 2 1 A B
b
C D E
k
C D
b
f
E
Top View (Bump Side Down)
Bottom View (Bump Side Up) Note: Drawing not to scale d = Die Orientation mark e
c Side View (Bump Side Down)
Ball Matrix
4 3 2 1
A B C D E
RL2 V3 WP SCL SDA
RW2 RH2 V3RO MR RL1
V1/VCC V1RO
NC NC
V2RO V2
NC
RH1 VSS
RW1
Millimeters Symbol Min Nom Max Min
Inches Nom Max
Package Body Dimension X Package Body Dimension Y Package Height Body Thickness Ball Height Ball Diameter Ball Pitch - X Axis Ball Pitch - Y Axis Ball to Edge Spacing - Distance Along X Ball to Edge Spacing - Distance Along Y
a b c d e f j k l m
2.524 3.794 0.654 0.444 0.210 0.316
2.554 3.824 0.682 0.457 0.225 0.326 0.5 0.5
2.584 3.854 0.710 0.470 0.240 0.336
0.09938 0.14938 0.02575 0.01748 0.00827 0.01244
0.10056 0.15056 0.02685 0.01799 0.00886 0.01283 0.01969 0.01969
0.10174 0.15174 0.02795 0.01850 0.00945 0.01323
0.497 0.882
0.527 0.912
0.557 0.942
0.01957 0.03473
0.02075 0.03591
0.02193 0.03709
28
FN8209.0 March 10, 2005
X9523
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.252 (6.4) .260 (6.6)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane (1.78)
(4.16) (7.72)
(0.42) (0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)
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FN8209.0 March 10, 2005
X9523
ORDERING INFORMATION X9523 Device P T
-y
Preset (Factory Shipped) VTRIPx Threshold Levels (x = 1,2,3) A = Optimized for 3.3V system monitoring B = Optimized for 5V system monitoring Temperature Range I = Industrial -40C to +85C
Package V20 = 20-Lead TSSOP B20 = 20-Lead XBGA
XBGA PART MARK CONVENTION
20 Lead XBGA Top Mark
X9523B20I-A X9523B20I-B
XACO XACS
For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 30
FN8209.0 March 10, 2005

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